1. Field of the Invention
The present invention relates to a configurable output buffer and method to provide differential drive.
2. Description of the Related Art
In Floating Programmable Gate Arrays (FPGAs) and in other integrated circuit devices, Low Voltage Differential Signal (LVDS) interfacing is widely used because of several advantages of the differential signaling and low output swing. The main advantage of LVDS is its high speed data transmission rate with reduced noise and reduced electro-magnetic interference (EMI).
FIG. 1 and FIG. 2 show schematic block diagrams for existing schemes of providing LVDS capabilities with other general-purpose I/O standards in programmable devices.
In FIG. 1, one LVDS receiver 70 is connected between two I/O pads 20 and 30. Pins 20 and 30 each have one conventional output buffer 60 and one conventional input buffer 50 to support general purpose I/O standards. Blocks 72, 52 and 62 are logic blocks that disable respective buffers. When differential input signals are required at pins 20 and 30, LVDS receiver 70 is enabled by logic circuit 72 while other blocks are disabled. Similarly, block 50 is activated for receiving single ended signal from pads 20 and 30, while block 60 is activated to give single ended outputs at pads 20 and 30.
In the scheme of FIG. 1, differential pins 20 and 30 can only support differential input mode and cannot operate in differential output mode. Pins 20 and 30 can independently support single ended input or output operations.
In FIG. 2, LVDS driver 600 is connected between two pads 20 and 30. Each of pads 20 and 30 incorporate one conventional output buffer 60 and one conventional input buffer 50. In the arrangement of FIG. 2, differential pins 20 and 30 can together support only differential output mode, while independently supporting single ended operation.